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Press Release

Cortus and Oryx Enable Internet of Things SoC Spplications

Oryx Embedded CycloneTCP dual IPv4/IPv6 stack ported to Cortus APS processor cores and Cortus Ethernet MAC

Cortus, a technology leader in low-power, silicon-efficient, 32-bit processor IP, and Oryx Embedded, an IT company specialised in middleware solutions, announced the availability of Oryx's CycloneTCP on Cortus' APS processor cores today. CycloneTCP is a dual IPv4 & IPv6 stack aimed at embedded applications. By supporting IPv6, Oryx CycloneTCP running on Cortus APS cores with the Cortus Ethernet 10/100 MAC enables the development of systems-on-chip (SoC) for both IoT edge devices and complex gateways.

"The Internet of Things and other emerging embedded applications require efficient processor cores, peripherals and software," said Clément Zeller, CEO at Oryx Embedded. "The Cortus APS processor family, combined with the Ethernet 10/100 MAC is a great complement to CycloneTCP for IoT and other embedded applications."

CycloneTCP is a dual IPv4/IPv6 stack dedicated to embedded applications. CycloneTCP conforms to RFC standards and offers seamless interoperability with existing TCP/IP systems. By supporting IPv6, CycloneTCP eases deployment of next-generation Internet. The stack is distributed as full ANSI C and highly maintainable source code. CycloneTCP is available either as open source (GPLv2) or under a commercial license.

"With a massively growing number of devices being connected to the internet, Cortus recognises the importance of IPv6," said Mr. Michael Chapman, CEO and President of Cortus, "SoC developments require software that has been optimised for embedded applications. We are delighted that Oryx Embedded is the first company to port an IPv6 stack to our APS cores."

Cortus licenses a range of low power, silicon efficient, 32-bit processor cores supporting a range computational performance and supporting different system complexity. The cores start from entry-level 32-bit cores suitable for upgrading 8-bit cores to cores supporting caches, co-processors and symmetric multiprocessing systems. They share the simple vectored interrupt structure, which ensures rapid, real time interrupt response, with low software overhead.

All APS processor cores interface to Cortus' peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. The Ethernet MAC allows the chosen physical interface to be connected using either the Medium Independent Interface (MII) or Reduced Medium Independent Interface (RMII). Flexible memory interfaces with two independent DMA channels enable system design to ensure low CPU overhead reception and transmission without any danger of frames being lost. Address filtering enables a single interface to respond to multiple MAC addresses.

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